View LTC4221-15_8941712.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ltc4221 4221fa dual hot swap controller/ power sequencer with dual speed, dual level fault protection allows safe board insertion and removal from a live backplane configurable power supply sequencing soft-start with current foldback limits inrush current no external gate capacitor required adjustable dual level circuit breaker protection controls supply voltages from 1v to 13.5v independent n-channel mosfet high side drivers fb pin monitors v out for overvoltage protection latch off or automatic retry on current fault fault and pwrgd outputs narrow 16-pin ssop package electronic circuit breaker power supply sequencing live board insertion and removal industrial high side switch/circuit breaker the ltc ? 4221 is a 2-channel hot swap tm controller that allows a board to be safely inserted and removed from a live backplane. using two independent high side gate drivers to control two external n-channel pass transistors, the output voltages can be ramped up with current foldback to limit the inrush current during the start-up period. no external compensation capacitors are required at the gate pins. the two channels can be configured to ramp up and down separately or simultaneously for supply volt- ages ranging from 2.7v to 13.5v and 1v to 13.5v for channels 1 and 2 respectively. each channel has two current limit comparators that provide dual level and dual speed overcurrent circuit breaker protection after the start-up period. if any current sense voltage exceeds 100mv for 1 s or 25mv for the timeout delay (set by the c filter at the filter pin), then the fault latch is set and both gate pins are pulled low. the fb pins monitor the respective channel output volt- ages and provide the inputs for the pwrgd comparators as well as overvoltage protection. hot swap is a trademark of linear technology corporation. 2-channel hot swap controller features descriptio u applicatio s u , ltc and lt are registered trademarks of linear technology corporation. typical applicatio u on2 fault gnd ltc4221 fb2 pwrgd2 pwrgd1 pwrgd2 v out1 3.3v/5a v out2 2.5v/5a pwrgd1 fb1 long long short gnd fault long *smaj10 (optional) short timer filter on1 v cc1 sense1 gate1 v cc2 sense2 gate2 short v cc1 3.3v v cc2 2.5v backplane connector (female) pcb edge connector (male) 10 21k 13.3k 10k 10k 10 14.3k irf7413 5.11k 10k 10k 20k 5.11k 4221 ta01 100nf * * 1nf 470nf 100nf irf7413 0.004 0.004
2 ltc4221 4221fa (note 1) supply voltage (v cc n ) ............................................ 17v sense n pins ............................ e 0.3v to (v cc n + 0.3v) fb, on pins .............................. e 0.3v to (v cc1 + 0.3v) timer pin .................................................. e 0.3v to 2v gate pins (note 3) ................................... e 0.3v to 21v pwrgd, fault, filter pins ................... e 0.3v to 17v operating temperature range ltc4221c ............................................... 0 c to 70 c ltc4221i ............................................ e 40 c to 85 c storage temperature range ................. e 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c t jmax = 125 c, v ja = 130 c/w absolute m axim u m ratings w ww u symbol parameter conditions min typ max units v cc1 supply voltage channel 1 2.7 13.5 v v cc2 supply voltage channel 2 v cc2 f v cc1 1 13.5 v i cc1 v cc1 supply current on1, on2 = 2v 2.2 3 ma i cc2 v cc2 supply current on1, on2 = 2v 0.05 0.15 ma v cc1(uvl) undervoltage lockout for channel 1 v cc1 rising 2.1 2.5 2.675 v ) v cc1(hyst) undervoltage lockout hysteresis 110 mv v cc2(uvl) undervoltage lockout for channel 2 v cc2 rising 0.65 0.8 0.975 v ) v cc2(hyst) undervoltage lockout hysteresis 25 mv i sense1(in) sense1 pin input current 0v f v sense1 f v cc1 0.03 5 r a i sense2(in) sense2 pin input current v sense2 = v cc2 0.2 5 r a v sense2 = 0v 1000 r a v sense(fc) sense n threshold voltage channel n fast comparator threshold 85 100 115 mv v sense(sc) sense n threshold voltage channel n slow comparator threshold 22.5 25 27.5 mv 20.5 25 29.5 mv v sense(acl) sense n voltage at active v fb n = 0 4 9 16 mv current limit v fb n = 0.65v 17.5 25 32.5 mv the indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc1 = 5v, v cc2 = 3.3v, unless otherwise noted. gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 on1 v cc1 sense1 gate1 fb1 pwrgd1 fault filter on2 v cc2 sense2 gate2 fb2 pwrgd2 gnd timer electrical characteristics lead free finish tape and reel part marking package description temperature range ltc4221cgn#pbf ltc4221cgn#trpbf 4221 16-lead plastic ssop 0 c to 70 c ltc4221ign#pbf ltc4221ign#trpbf 4221i 16-lead plastic ssop e40 c to 85 c lead based finish tape and reel part marking package description temperature range ltc4221cgn ltc4221cgn#tr 4221 16-lead plastic ssop 0 c to 70 c ltc4221ign ltc4221ign#tr 4221i 16-lead plastic ssop e40 c to 85 c consult ltc marketing for parts specified with wider operating temperature ranges. order i for atio uu w pi co figuratio uuu for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3 ltc4221 4221fa symbol parameter conditions min typ max units i gate(up) gate n output current v on1 = v on2 = 2v, v gate n = 0v C7 C9.5 C12 a i gate(dn) gate n output current v on1 = v on2 = 0.6v, v gate n = 3.3v 75 100 125 a i gate(fstdn) gate n output current uvlo with v gate n = 3.3v or fault 16 ma latched with v gate n = 3.3v v gate external n-channel gate drive v gate n C v cc1 for v cc1 = 2.7v, v cc2 = 1v 4.5 13 v v gate n C v cc1 for v cc1 = 3.3v, v cc2 = 2.5v 516v v gate n C v cc1 for v cc1 = 5v, v cc2 = 3.3v 816v v gate n C v cc1 for v cc1 = 12v, v cc2 = 12v 718v v gate(ov) gate n overvoltage lockout threshold 0.4 0.5 v i on(in) on n pin input current 0v v on n v cc1 0.01 1 a v on(reset) on1 reset threshold v on1 falling 0.375 0.4 0.425 v v on(resethyst) on1 reset threshold hysteresis 25 mv v on(off) on n off threshold high to low, gate n turns off by 100 a 0.796 0.821 0.846 v pull-down v on(offhyst) on n off threshold hysteresis 30 mv i fb(in) fb n input current 0v v fb n v cc n 0.01 1 a v fb(uv) fb n undervoltage threshold fb n falling 0.605 0.617 0.629 v v fb(uvhyst) fb n undervoltage threshold hysteresis 3 mv v fb(lreg) fb n threshold line regulation 2.7v v cc1 13.5v 2 mv v fb(ov) fb n overvoltage threshold fb n rising 0.805 0.822 0.838 v i filter(up) filter pull-up current during current fault condition C80 C105 C132 a i filter(dn) filter pull-down current during normal cycle 1.15 1.8 2.45 a v filter(th) filter threshold latched off threshold, filter rising 1.18 1.24 1.30 v v filter(hyst) filter threshold hysteresis 105 mv i tmr(up1) timer pull-up current 1 initial timing cycle C1.2 C1.9 C2.6 a i tmr(up2) timer pull-up current 2 start-up cycle C15 C20 C25 a i tmr(fstdn) timer pull-down current v timer = 1.5v, end of initial timing cycle 9 ma v tmr(h) timer high threshold timer rising 1.172 1.234 1.27 v v tmr(l) timer low threshold timer falling 0.1 0.4 0.5 v i fault(up) fault pull-up current C2.5 C3.8 C5 a v fault(th) fault threshold fault falling 0.791 0.816 0.841 v v fault(hyst) fault hysteresis 35 mv v fault(ol) fault output low voltage i fault = 1.6ma, v cc1 = 5v 0.14 0.4 v i pwrgd(lk) pwrgd n leakage current v pwrgd n = v cc1 , v fb n = 0.7v, normal cycle 0.01 10 a v pwrgd(ol) pwrgd n output low voltage i pwrgd n = 1.6ma, v cc1 = 5v, v fb n = 0v, 0.14 0.4 v normal cycle t p(fc-gate) fast comparator trip to gate n v sense n = v cc n to (v cc n C 200mv) step 1 1.5 s discharging t p(sc-fault) slow comparator trip to filter v sense n = v cc n to (v cc n C 50mv) step. 15 35 s high and fault latched filter open the indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc1 = 5v, v cc2 = 3.3v, unless otherwise noted. electrical characteristics
4 ltc4221 4221fa typical perfor a ce characteristics uw i cc1 vs temperature temperature ( c) C50 i cc1 (ma) 4 5 6 25 75 4221 g01 3 2 C25 0 50 100 125 1 0 v cc2 = 1v v cc1 = 13.5v v cc1 = 12v v cc1 = 5v v cc1 = 2.7v temperature ( c) C50 i cc2 (ma) 0.175 25 4221 g02 0.100 0.050 C25 0 50 0.025 0 0.200 0.150 0.125 0.075 75 100 125 v cc1 = 13.5v v cc2 = 13.5v v cc2 = 12v v cc2 = 5v v cc2 = 3.3v v cc2 = 1v temperature ( c) C50 v cc1(uvl) (v) 2.50 25 4221 g03 2.44 2.40 C25 0 50 2.38 2.36 2.52 2.48 2.46 2.42 75 100 125 timer = 0.3v rising falling i cc2 vs temperature v cc1(uvl) vs temperature v cc2(uvl) vs temperature |i sense2(in) | vs v sense2 v sense(fc) vs v cc1 temperature ( c) C50 0.770 v cc2(uvl) (v) 0.775 0.785 0.790 0.795 50 0.815 4221 g04 0.780 0 C25 75 100 25 125 0.800 0.805 0.810 timer = 0.3v rising falling v sense2 (v) 0 |i sense2(in) | ( a) 1000 6 4221 g05 1 0.01 24 8 0.001 0.0001 10000 100 10 0.1 10 12 v cc1 = 2.7v, v cc2 = 1v v cc1 = 5v, v cc2 = 3.3v v cc1 = 13.5v, v cc2 = 13.5v v cc1 (v) 0 v sense(fc) (mv) 101.0 101.5 102.0 610 16 4221 g06 100.5 100.0 99.5 24 8 12 14 v cc2 = v cc1 t a = 25 c note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: all current into device pins are positive. all voltages are referenced to ground unless otherwise specified. note 3: an internal zener on each gate pin clamps the charge pump voltage to a typical maximum operating voltage of 26v. external overdrive of either gate pin beyond its internal zener voltage may damage the device. the indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc1 = 5v, v cc2 = 3.3v, unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units t p(fault-gate) fault low to gate n discharging v fault = 3.3v to 0v 15 35 s t p(ov-gate) fb n ov comparator trip to gate n v fb n = 0v to 1v 18 35 s discharging t p(filter-gate) filter comparator trip to gate n v filter = 0v to 1.5v 15 35 s discharging t reset circuit breaker reset delay time v on1 < 0.4v to fault high 15 30 s t p(on-gate) turn off propagation delay v on n 0.821v to gate n discharging 15 35 s
5 ltc4221 4221fa typical perfor a ce characteristics uw v sense(acl) vs v fb i gate(up) vs temperature i gate(dn) vs temperature i gate(fstdn) vs temperature v gate n (v gate n ?v cc1 ) vs v cc1 v fb (v) 0 v sense(acl) (mv) 20 25 30 0.3 0.5 4221 g10 15 10 0.1 0.2 0.4 0.6 0.7 5 0 v cc1 = 5v v cc2 = 3.3v t a = 25 c temperature ( c) C50 i gate(up) ( a) C8 C7 C6 25 75 4221 g11 C9 C10 C25 0 50 100 125 C11 C12 v cc1 = 2.7v v cc1 = 5v v cc1 = 13.5v v cc2 = 1v v gate = 0v temperature ( c) C50 101 102 104 25 75 4221 g12 100 99 C25 0 50 100 125 98 97 103 i gate(dn) ( a) v cc1 = 2.7v v cc1 = 5v v cc1 = 13.5v v cc2 = 1v v gate = 3.3v temperature ( c) C50 i gate(fstdn) (ma) 40 50 60 25 75 4221 g13 30 20 C25 0 50 100 125 10 0 v cc1 = 2.7v v cc1 = 5v v cc1 = 13.5v v cc2 = 1v v gate = 3.3v v cc1 (v) 0 6 v gate n (v) 7 9 10 11 8 15 4221 g14 8 4 2 10 12 614 12 13 14 v cc2 = v cc1 C 1.5v t a = 25 c v gate1 v gate2 v gate1 (v gate1 ?v cc1 ) vs temperature temperature ( c) C50 12 14 18 25 75 4221 g15 10 8 C25 0 50 100 125 6 4 16 v gate1 (v) v cc1 = 2.7v, v cc2 = 1v v cc1 = 5v, v cc2 = 3.3v v cc1 = 13.5v, v cc2 = 13.5v v sense(fc) vs temperature v sense(sc) vs v cc1 v sense(sc) vs temperature temperature ( c) C50 v sense(fc) (mv) 101.0 101.5 102.0 25 75 4221 g07 100.5 100.0 C25 0 50 100 125 99.5 99.0 v cc1 = 5v v cc2 = 3.3v v cc1 (v) 0 v sense(sc) (mv) 25.0 25.2 25.4 12 4221 g08 24.8 24.6 48 214 610 16 24.4 24.2 25.6 v cc2 = v cc1 t a = 25 c temperature ( c) C50 v sense(sc) (mv) 25.8 25 4221 g09 25.2 24.8 C25 0 50 24.6 24.4 26.0 25.6 25.4 25.0 75 100 125 v cc1 = 5v v cc2 = 3.3v
6 ltc4221 4221fa typical perfor a ce characteristics uw v on(reset) vs temperature v on(off) vs v cc1 v on(off) vs temperature temperature ( c) C50 0.395 v on(reset) (v) 0.405 0.410 0.415 50 0.440 4221 g19 0.400 0 C25 75 100 25 125 0.425 0.420 0.430 0.435 v cc1 = 5v v cc2 = 3.3v rising falling v cc1 (v) 0 v on(off) (v) 0.840 0.845 0.850 16 4221 g20 0.835 0.830 0.815 4 8 12 2 6 10 14 0.825 0.820 0.860 0.855 v cc2 = 1v t a = 25 c rising falling temperature ( c) C50 v on(off) (v) 0.85 0.86 0.87 25 75 4221 g21 0.84 0.83 C25 0 50 100 125 0.82 0.81 v cc1 = 5v v cc2 = 3.3v rising falling v fb(uv) vs v cc1 v fb(uv) vs temperature v fb(ov) vs v cc1 v cc1 (v) 0 v fb(uv) (v) 0.618 0.620 16 4221 g22 0.616 0.614 4 8 12 2 6 10 14 0.622 0.617 0.619 0.615 0.621 v cc2 = 1v t a = 25 c rising falling temperature ( c) C50 v fb(uv) (v) 0.623 0.622 0.621 0.620 0.619 0.618 0.617 0.616 0.615 0.614 0.613 0 50 75 4221 g23 C25 25 100 125 v cc1 = 5v v cc2 = 3.3v rising falling v cc1 (v) 0 v fb(ov) (v) 0.8210 0.8215 0.8220 12 4221 g24 0.8205 0.8200 48 214 610 16 0.8195 0.8190 0.8225 v cc2 = 1v t a = 25 c v gate(ov) vs temperature v on(reset) vs v cc1 v gate2 (v gate2 ?v cc1 ) vs temperature temperature ( c) C50 v gate2 (v) 12 14 16 25 75 4221 g16 10 8 C25 0 50 100 125 6 4 v cc1 = 2.7v, v cc2 = 1v v cc1 = 5v, v cc2 = 3.3v v cc1 = 13.5v, v cc2 = 13.5v temperature ( c) C50 0.375 v gate(ov) (v) 0.385 0.390 0.395 50 0.420 4221 g17 0.380 0 C25 75 100 25 125 0.405 0.400 0.410 0.415 v cc1 = 2.7v v cc1 = 5v v cc1 = 13.5v v cc2 = 1v timer = 0.5v v cc1 (v) 0 v on(reset) (v) 0.415 0.420 0.425 12 4221 g18 0.410 0.405 48 214 610 16 0.400 0.395 0.430 v cc2 = 1v, t a = 25 c falling rising
7 ltc4221 4221fa typical perfor a ce characteristics uw v filter(th) vs temperature i tmr(up1) vs temperature temperature ( c) C50 v filter(th) (v) 1.246 1.244 1.242 1.240 1.238 1.236 1.234 1.232 1.230 1.228 1.226 1.224 0 50 75 4221 g28 C25 25 100 125 v cc1 = 2.7v v cc1 = 5v v cc1 = 13.5v v cc2 = 1v v gate1 = 0.2v temperature ( c) C50 i tmr(up1) ( a) C1.8 C1.7 C1.6 25 75 4221 g29 C1.9 C2.0 C25 0 50 100 125 C2.1 C2.2 v cc1 = 2.7v v cc1 = 5v v cc1 = 13.5v v cc2 = 1v v tmr = 0.25v i tmr(up2) vs temperature temperature ( c) C50 i tmr(up2) ( a) C17.0 C17.5 C18.0 C18.5 C19.0 C19.5 C20.0 C20.5 C21.0 C21.5 C22.0 0 50 75 4221 g30 C25 25 100 125 v cc1 = 2.7v v cc1 = 5v v cc1 = 13.5v v cc2 = 1v v tmr = 0.25v i tmr(fstdn) vs temperature v tmr(h) vs temperature temperature ( c) C50 C25 0 i tmr(fstdn) (ma) 10 25 0 50 75 4221 g31 5 20 15 25 100 125 v cc1 = 2.7v v cc1 = 5v v cc1 = 13.5v v cc2 = 1v v tmr = 1.5v temperature ( c) C50 v tmr(h) (v) 1.240 1.238 1.236 1.234 1.232 1.230 1.228 1.226 1.224 1.222 1.220 0 50 75 4221 g32 C25 25 100 125 v cc1 = 2.7v v cc1 = 5v v cc1 = 13.5v v cc2 = 1v v tmr(l) vs temperature temperature ( c) C50 v tmr(l) (v) 0.403 25 4221 g33 0.400 0.398 C25 0 50 0.397 0.396 0.404 0.402 0.401 0.399 75 100 125 v cc1 = 2.7v v cc1 = 5v v cc1 = 13.5v v cc2 = 1v v fb(ov) vs temperature i filter(up) vs temperature temperature ( c) C50 v fb(ov) (v) 0.825 0.824 0.823 0.822 0.821 0.820 0.819 0.818 0.817 0.816 0.815 0 50 75 4221 g25 C25 25 100 125 v cc1 = 5v v cc2 = 3.3v temperature ( c) C50 i filter(up) ( a) C98 C93 C88 25 75 4221 g26 C103 C108 C25 0 50 100 125 C113 C118 v cc1 = 2.7v v cc1 = 5v v cc1 = 13.5v v cc2 = 1v v filter = 1v i filter(dn) vs temperature temperature ( c) C50 1.85 1.90 2.00 25 75 4221 g27 1.80 1.75 C25 0 50 100 125 1.70 1.65 1.95 i filter(dn) ( a) v cc1 = 2.7v v cc1 = 5v v cc1 = 13.5v v cc2 = 1v v filter = 1v
8 ltc4221 4221fa uu u pi fu ctio s on1 (pin 1): system/channel 1 on input. both gate pins are pulled low by internal 100 a pull-downs and the fault latch is reset when v on1 < 0.4v. when 0.425v < v on1 < 0.821v, the fault latch is released from reset. when v on1 > 0.851v, gate1 ramps up after an initial timing cycle. v cc1 (pin 2): channel 1 positive supply input. it powers all the internal circuitry. v cc1 can range from 2.7v to 13.5v for normal operation but it must be v cc2 . an undervolt- age lockout circuit disables both channels whenever the voltage at v cc1 is less than 2.5v. sense1 (pin 3): channel 1 current sense input. a sense resistor r sense1 is placed in the supply path between v cc1 and sense1 to sense channel 1 load current. if v rsense1 exceeds 100mv for more than 1 s or 25mv for an adjust- able time (set by the c filter ), the fault latch is set and fast pull-down circuits are triggered to discharge both gates low. during the start-up cycle, gate1 ramp-up is controlled to servo v rsense1 v sense(acl) . v sense(acl) increases from 9mv to 25mv as v fb1 ramps from 0v to 0.5v. to disable the current limit and circuit breaker function for channel 1, tie sense1 to v cc1 . typical perfor a ce characteristics uw v pwrgd(ol) /v fault(ol) vs temperature tp (sc-fault) vs temperature temperature ( c) C50 v ol (v) 0.500 0.450 0.400 0.350 0.300 0.250 0.200 0.150 0.100 0.050 0 0 50 75 4221 g37 C25 25 100 125 v cc1 = 2.7v v cc1 = 5v v cc1 = 13.5v v cc2 = 1v, i pwrgd /i fault = 1.6ma tp (fc-gate) vs temperature temperature ( c) C50 tp (sc-fault) ( s) 16 17 18 25 75 4221 g38 15 14 C25 0 50 100 125 13 12 v cc1 = 2.7v v cc1 = 5v v cc1 = 13.5v v cc2 = 1v timer = 0.5v temperature ( c) C50 tp (fc-gate) ( s) 1.4 1.6 1.8 25 75 4221 g39 1.2 1.0 C25 0 50 100 125 0.8 0.6 v cc1 = 2.7v v cc1 = 5v v cc1 = 13.5v v cc2 = 1v timer = 0.5v i fault(up) vs temperature v fault(th) vs v cc1 v fault(th) vs temperature temperature ( c) C50 C3.7 C3.5 C3.1 25 75 4221 g34 C3.9 C4.1 C25 0 50 100 125 C4.3 C4.5 C3.3 i fault(up) ( a) v cc1 = 2.7v v cc1 = 5v v cc1 = 13.5v v cc2 = 1v v fault = 1.5v v cc1 (v) 0 0.810 v fault(th) (v) 0.815 0.825 0.830 0.835 0.860 0.845 4 8 10 4221 g35 0.820 0.850 0.855 0.840 26 12 14 16 v cc2 = 1v t a = 25 c rising falling temperature ( c) C50 0.84 0.85 0.87 25 75 4221 g36 0.83 0.82 C25 0 50 100 125 0.81 0.80 0.86 v fault(th) (v) v cc1 = 5v v cc2 = 3.3v rising falling
9 ltc4221 4221fa uu u pi fu ctio s gate1 (pin 4): channel 1 gate drive. this pin is the high side gate drive of an external n-channel mosfet. when v on1 < 0.821v, gate1 is held low by a 100 a current source. when v on1 > 0.851v, an initial timing cycle is followed by a start-up cycle when an internal charge pump provides a 9.5 a pull-up to ramp up gate1 with inrush current limiting. uvlo, overvoltage, overcurrent and ex- ternally generated faults override the on1 pin and pull gate1 low. fb1 (pin 5): v out1 feedback input. fb1 monitors the channel 1 output voltage with an external resistive divider. when v fb1 < 0.617v, the pwrgd1 pin is pulled low. when v fb1 > 0.822v, overvoltage is detected, the fault latch is set and both gates are pulled low. the fb1 pin is also used to control the channel 1 current limit during its start-up cycle. pwrgd1 (pin 6): channel 1 power good output. pwrgd1 is pulled low when v fb1 < 0.617v, during the initial timing cycle or when the chip is in uvlo. an external pull-up is required to generate a logic high at the open-drain pwrgd1 pin. fault (pin 7): fault status input/output. fault is a bidirectional pin. as an input, pulsing v fault < 0.816v will set the fault latch and bring the ltc4221 into the fault state. as an output, fault is pulled high by an internal 3.8 a pull-up under normal operating conditions. when an overcurrent fault is detected by a sense pin or a overvoltage fault detected by an fb pin, the fault latch is set and the ltc4221 goes into the fault state. the fault latch is reset by a uvlo or the on1 pin being driven below 0.4v. filter (pin 8): overcurrent fault timing filter. the filter pin requires an external capacitor to ground to adjust the response time of the two slow comparators. the filter pin can be left unconnected for a default slow comparator response time of 15 s. timer (pin 9): analog system timer. the timer pin requires an external capacitor to ground to generate timing delay cycles during start-up. the ltc4221s initial and start-up timing cycles are controlled by c timer and the internal current sources connected to the timer pin. gnd (pin 10): ground. connect to a ground plane for optimum performance. pwrgd2 (pin 11): channel 2 power good output. similar functionality as pwrgd1. controlled by fb2. fb2 (pin 12): v out2 feedback input. similar functionality as fb1. monitors channel 2 output voltage, controls pwrgd2 output and channel 2 start-up current limit. gate2 (pin 13): channel 2 gate drive. similar functional- ity as gate1. controls the gate drive of the channel 2 external n-channel mosfet. on2 controls gate2 in the same manner as on1 controls gate1. v on1 < 0.4v over- rides conditions at on2 and gate2 is held low by a 100 a current source. uvlo, overvoltage, overcurrent and exter- nally generated faults override conditions at on1 and on2, and pull gate2 low. sense2 (pin 14): channel 2 current sense input. similar functionality as sense1. monitors channel 2 load current through r sense2 placed in the supply path between v cc2 and sense2. to disable the current limit and circuit breaker function for channel 2, tie sense2 to v cc2 . v cc2 (pin 15): channel 2 positive supply input. v cc2 can range from 1v to 13.5v for normal operation but it must be v cc1 . an undervoltage lockout circuit disables both channels whenever the voltage at v cc2 is less than 0.8v. on2 (pin 16): channel 2 on input. gate2 is pulled to ground by a 100 a current source when v on2 < 0.821v. when v on2 > 0.851v, gate2 ramps up after an initial timing cycle.
10 ltc4221 4221fa block diagra w 26v 9.5 a 100 a cpo2 v cc2 cur_limit2 fpd2 + C charge pump 1 charge pump 2 uvlo oscillator v cc1 v cc1 v cc2 cpo1 cpo2 0.821v on1 comparator system control logic 0.4v v cc1 1 on1 + C on2 comparator filter comparator tmrhi comparator fault comparator 0.821v ftrhi tmrhi timer 1.234v fault_lo 105 a 1.8 a + C + C 1.24v 0.816v + C 0.617v + C ov1 comparator fb1 comparator 0.822v + C 16 9 on2 8 filter v cc1 3.8 a v cc1 v cc1 fault 7 gnd 10 gate1 26v pwrgd1 channel one 20 a1.9 a v cc1 v cc1 9.5 a 12v 12v 100 a cpo1 v cc1 cur_limit1 fpd1 tmrlo comparator tmrlo 0.4v + C + C slow comparator 1 channel 1 control logic slowhi1 9mv to 25mv fasthi1 2 v cc1 + C fast comparator 1 gatelo1 comparator gatelo1 0.4v + C sense1 + C v cc1 100mv + C 3 fb1 5 6 4 0.617v + C ov2 comparator fb2 comparator 0.822v + C v cc2 gate2 pwrgd2 4221 bd channel two + C slow comparator 2 channel 2 control logic slowhi2 9mv to 25mv fasthi2 15 v cc2 + C fast comparator 2 gatelo2 comparator gatelo2 0.4v + C sense2 + C v cc2 100mv + C 14 fb2 12 11 13
11 ltc4221 4221fa hot circuit insertion when circuit boards are inserted into a live backplane, the supply bypass capacitors can draw huge transient cur- rents from the power bus as they charge. the flow of current may damage the connector pins and glitch the power bus, causing other boards in the system to reset. the ltc4221 is designed to turn on and off a circuit boards supply voltages in a controlled manner, allowing insertion or removal without glitches or connector dam- age. the ltc4221 can reside on the backplane or on the removable circuit board for hot insertion applications. it controls the path between the backplane power bus and the daughter board load with an external mosfet switch. both inrush control and short-circuit protection are pro- vided by the external mosfet. each ltc4221 controls two channels, each with its individual mosfet for sup- plies from 1v to 13.5v. overview the timing diagram in figure 1 shows some typical wave- forms of the ltc4221. the v cc and gnd pins receive power through the longest connector pins and are the first to connect when the board is inserted. during the under- voltage lockout (uvlo) state before time point 1, both gate pins are held low by internal n-channel mosfet pull-downs, turning the external mosfets off. once both v cc pins are valid at time point 1, the ltc4221 enters into a reset state as on1 is below its reset threshold. at time point 2, on1 clears its reset threshold and the device goes from the reset state to an off state. when either on1 or on2 clears its off threshold, both gate pins are < 0.4v and timer < 0.4v (time points 3 and 4), the timer pin sources 1.9 a and an initial timing cycle starts. any transition of on1 and on2 through their off thresholds will reset the initial timing cycle. at time point 5, timer reaches its high threshold and is pulled down by an internal n-channel mosfet to its low threshold at time point 6. the ltc4221 then checks that filter pin voltage is low and fault pin voltage is high. if both conditions are met, the electronic circuit breaker is armed. the channel 1 start-up timing cycle starts at time point 6 since on1 has cleared its off threshold and on2 has not. operatio u during the start-up cycle, timer sources 20 a and gate1 sources 9.5 a. as gate1 ramps up, mosfet1 starts to turn on and current flows through to charge up the load capacitance. as v out1 and fb1 ramp up, the load current is monitored through the external sense1 resistor. be- tween time points 7 and 8, the gate1 9.5 a pull-up is controlled to servo the voltage across r sense1 to be less than the sense1 active current limit voltage, which has a component controlled by the fb1 voltage (see applica- tions information: start-up cycle with current limit). in this way, inrush current is limited and mosfet1 does not overheat during the start-up cycle. when fb1 clears its undervoltage threshold, pwrgd1 asserts high. at time point 9, timer reaches its high threshold and is pulled down by an internal n-channel mosfet to its low thresh- old at time point 10. channel 1s slow comparator is armed at time point 9 and enters a fault monitor mode, bringing the channel 1 start-up cycle to an end. at time point 10, on2 voltage is monitored and since on2 has cleared its off threshold, the start-up timing cycle repeats for channel 2. the inrush current is low and gate2 ramps up without need for current limiting. channel 2s slow comparator is armed at time point 11 and enters a fault monitor mode, ending the channel 2 start-up cycle. overcurrent faults translate to an increase in either v rsense . at time point 13, v rsense1 > 25mv (slow comparator threshold). the 1.8 a pull-down on the filter changes to a 105 a pull-up. when the filter pin hits its threshold at time point 14, it triggers a fault state when fault is latched low and both gate pins are pulled low by internal n-channel mosfets, turning off the external mosfets. as each channel output discharges, its fb pin goes below the undervoltage threshold and the pwrgd pin deasserts. higher overcurrents when either v rsense > 100mv (fast comparator threshold) for more than 1 s will trigger the same condition. this fault state can only be cleared by a uvlo at either v cc pin or a hard reset at the on1 pin, as at time point 15, when on1 is pulled below its reset threshold. the ltc4221 then reverts back to its reset state as between time points 1 and 2.
12 ltc4221 4221fa operatio u v cc n timer fault filter on1 v on(off) + v on(offhyst) v on(reset) + v on(resethyst) v on(off) v gate(ov) v on(off) + v on(offhyst) on2 gate1 gate2 sense1 sense2 v out1 v out2 pwrgd1 pwrgd2 uvlo off initial timing reset 100 a 100 a v cc n (uvl) 1 v cc n clears v cc n (uvl) electronic circuit breaker armed, check filter < v filter(th) , fault > v fault(th) + v fault(hyst) on1 > v on(reset) + v on(resethyst) channel 1 slow comparator armed on2 > v on(off) , + v on(offhyst) , check gate < v gate(ov) , timer < 0.4v on1 > v on(off) + v on(offhyst) , check gate < v gate(ov) , timer < 0.4v 2 channel 2 slow comparator armed 3 4 5 6 7 8 9 10 11 12 13 14 15 1.9 a v tmr(h) v tmr(l) 20 a20 a 1.8 a v filter(th) 105 a v on1(reset) v gate(ov) 9.5 a 9.5 a 25mv 9mv 9mv v sense(fc) v sense(sc) fb1 > v fb(uv) + v fb(hyst) fb1 < v fb(uv) fb2 < v fb(uv) fb2 > v fb(uv) + v fb(hyst) channel 1 start-up channel 2 start-up normal fault reset 4221 f01 figure 1. ltc4221 operation
13 ltc4221 4221fa applicatio s i for atio wu uu undervoltage lockout an internal undervoltage lockout (uvlo) occurs if either v cc supply is too low for normal operation. the ltc4221 is kept in lockout mode in which the internal charge pumps are off, the gate pins, timer are held low by internal n-channel mosfet pull-downs and the fault latch reset, cutting off both channels. v cc1 has a low-to-high uvlo threshold of 2.5v with 110mv hysteresis. v cc2 has a low- to-high uvlo threshold of 0.8v with 25mv hysteresis. both uvlos have glitch filters that filter out dips that are less than 30 s, allowing for bus supply transients. an additional requirement for normal operation is v cc1 v cc2 . on pin functions the on1 pin serves as a global reset for the ltc4221. it has an internal reset comparator with a high-to-low thresh- old of 0.4v, a 25mv hysteresis and a high-to-low glitch filter of 15 s. pulling on1 below this threshold will put the ltc4221 into a reset state in which the timer is pulled low by an internal n-channel mosfet pull-down, the gate pins are pulled low by separate internal 100 a pull-downs and the fault latch resets. a low-to-high transition on the on1 pin past the reset threshold releases the reset on the fault latch and both channels go into an off state. in addition to its global reset function, on1 also serves as an on/off switch for channel 1. on2 performs the same role for channel 2. both pins have an off comparator with a high-to-low threshold of 0.821v and 30mv hysteresis. with these, on1 and on2 can be used to force a simulta- neous or sequential power-up/power-down of the two channels. a simultaneous power-up and power-down is shown in figure 2b. both v cc pins clear their respective uvlo at time point 1 and both channels enter reset state. when on1 clears its reset threshold, either on1 or on2 clears its off threshold, both gates < 0.4v and timer < 0.4v (time point 2), an initial timing cycle starts. at time point 4, the initial timing cycle completes and the ltc4221 checks that filter is low and fault is high. if both conditions are met, it then monitors the voltage of on1 and on2. as long as its on pin has cleared its off threshold, each channel powers up regardless of the state of the other channel. similarly, if its on pin goes below its off thresh- old, each channel pulls its gate pin down with an internal 100 a pull-down and turns off its external mosfet re- gardless of the state of the other channel. as the circuit in figure 2a has its two on pins shorted together, a simulta- neous power-up is programmed at time points 4 to 5 and a simultaneous power down is programmed between time points 7 and 8. the timing waveforms in figure 3 show a + v cc1 on1 sense1 on2 r f2 15k ltc4221* gate1 fb1 4221 f02a 4221 f02b 1 16 10 9 c timer 1 f gnd timer (2a) circuit (2b) timing waveforms r f1 56k v out1 3.3v 5a v out2 2.5v 5a q1 irf7413 r sense1 0.004 c load1 z1 z1 = smaj10 * additional details omitted for clarity r x1 10 c x1 100nf r1 10k r2 10k long v cc1 long pcb edge connector (male) short backplane connector (female) long v cc2 discharge by load 1 v cc n v out n on n gate n uvlo initial timing channel start-up reset state timer 0.851v 1.234v 0.821v 9.5 a 100 a v th 20 a 234 56 78 normal reset v cc n (uvl) 1.9 a figure 2. simultaneous power on/off
14 ltc4221 4221fa sequential power up from time points 4 to 8 and a sequential power-down programmed from time points 9 to 11. to achieve this the circuit requires the functionality of the pwrgd1 pin and will be featured in the next section. the circuit in figure 2a sits on a daughter board with staggered pins on its edge connectors. supply voltage and ground connections are wired to long-edge connector pins while both on pins are connected to a short-edge connector pin through a resistive divider. until the con- nectors are fully mated, on1 is pulled low and holds both channels in the reset state. when the connectors have properly seated, the on pins are pulled above 0.851v and an initial timing cycle starts. this cycle is restarted by any transitions on the on pins across their off thresholds and adds a further delay for the plug-in transients to die off before allowing a start-up cycle. the typical application circuit on the first page of this data sheet shows similar considerations in the design of its pcb edge connectors, and the resistive dividers connected to on1 and on2 act as an external uvlo to override the internal one. an rc filter can be added at the on1 pin to increase the delay time at card insertion to allow bus supply transients to stabilize. fb and pwrgd pin functions each fb pin is used to detect undervoltage and overvoltage in its channel output voltage (v out ) through a resistive divider. each fb pin has an undervoltage comparator with a high-to-low threshold of 0.617v and 3mv hysteresis. the output of this comparator controls the channels open-drain pwrgd output. during uvlo, both pwrgd pins are pulled low by internal n-channel mosfet pull- downs. as both channels come out of uvlo, control of pwrgd1 is passed to fb1and control of pwrgd2 to fb2. each pwrgd pin can be connected to a pull-up resistor to 0.821v 100 a v cc n 12 34 5 67 8 91011 on1 timer gate1 v out1 pwrgd1 on2 gate2 uvlo initial timing reset v out2 v cc n (uvl) 0.851v 0.821v 0.4v 1.234v 20 a 100 a discharge by load discharge by load 4221 f03 20 a 9.5 a 9.5 a v th 0.851v v th v fb1 = 0.620v v fb1 = 0.617v channel 1 start-up channel 2 start-up channel 1 off channel 2 normal normal off 1.9 a applicatio s i for atio wu uu figure 3. sequential power on/off timing waveforms
15 ltc4221 4221fa generate a logic high output to indicate that v out is valid. an internal high-to-low glitch filter helps to prevent nega- tive voltage transients on each fb pin from deasserting its pwrgd. the relationship between glitch filter time and an fb pin transient voltage is shown in figure 4. using the functionality of the pwrgd1 pin, the ltc4221 can be configured to do sequential power-up and power-down as shown by the circuit in figure 5. referring back to figure 3, on2 is held low until v out1 ramps high enough for fb1 to exceed its undervoltage threshold at time point 5 when pwrgd1 ramps up, pulling on2 high. at time point 7, the control logic sees on2 exceeding its off threshold and so commences a start-up cycle for channel 2. similarly, when on1 is forced low by q2 at time point 9, gate1 is pulled low by its 100 a pull-down while on2 is held high by the r4 pull-up on pwrgd1. its is only when channel 1 is powered off and v out1 discharges below its undervoltage threshold at time point 10 that pwrgd1s internal n-channel mosfet pull-down is triggered and on2 goes low. at time point 11, on2 trips its off threshold and gate2 pulls low with a 100 a pull-down, powering off channel 2. for v out overvoltage detection, each fb pin has an over- voltage comparator with a low-to-high threshold of 0.822v and a low-to-high glitch filter of 18 s. this threshold is designed to be 33% higher than the undervoltage thresh- old. if either fb pin trips this threshold, the fault latch is set, all gate pins are pulled low with internal nfet pull-downs and the ltc4221 goes into a fault state. in the third function, each fb pin is used to control its channels current limit during its start-up cycle. this will be featured in the start-up cycle with current limit section. gate pin functions each gate pin controls the gate of its channels external n-channel mosfet. individual internal charge pumps powered by v cc1 guarantee a gate drive of minimum 4.5v and maximum 18v (internally clamped) for gate1 and gate2. during uvlo, the internal charge pumps are off and both gate pins are pulled low by internal n-channel mosfet pull-downs. outside uvlo, when on1 is below its off threshold, the charge pumps are on and gate1 is held low by an internal 100 a current pull-down. once applicatio s i for atio wu uu + v cc1 on1 sense1 on2 pwrgd1 r f2 15k ltc4221* gate1 fb1 4221 f05 1 16 6 10 9 c timer 1 f gnd timer r f1 56k v out1 3.3v 5a v out2 2.5v 5a q1 irf7413 r sense1 0.004 c load1 z1 q2: 2n7002lt1 z1: smaj10 * additional details omitted for clarity r x1 10 c x1 100nf r4 10k r2 2k q2 r1 10k r6 10k r5 10 r3 10k long v cc1 long pcb edge connector (male) short short backplane connector (female) long v cc2 on/off figure 5. using pwrgd1 to configure sequential power-up/power-down feedback transient (mv) glitch filter time ( s) 40 60 80 20 50 70 30 10 0 0 20 40 60 80 100 120 140 160 180 200 4221 f04 t a = 25 c figure 4. fb comparator glitch filter time vs feedback transient voltage
16 ltc4221 4221fa on1 clears its off threshold and the initial timing cycle is complete, the gate1 pin is pulled up by a 9.5 a current source connected to the charge pump output during the channel start-up cycle. gate1 can be servoed by adjusting the ramp up current to <9.5 a to control the inrush current to the load during start-up. on2 controls gate2 in a similar manner but is overwritten by on1s global reset function. during an overcurrent fault condition that sets the fault latch, both gate pins are pulled down by their respective internal n-channel mosfet pull-downs. during hot insertion of the pcb, an abrupt application of supply voltage charges the external mosfet drain/gate capacitance. this can cause an unwanted gate voltage spike. an internal proprietary circuit holds both gate pins low before the internal circuitry wakes up. this reduces the mosfet current surges substantially at insertion. electronic circuit breaker the ltc4221 features an electronic circuit breaker func- tion that protects against supply overvoltage, externally generated fault conditions and shorts or excessive load current conditions on any of the supplies. if the circuit breaker trips, both gate pins are immediately pulled to ground, the external n-channel mosfets are quickly turned off and fault is latched low. during the normal cycle, a supply overvoltage on channel n propagates via the v out n resistive dividers to the fb n pin. a supply overvoltage high enough to pull either fb pin above 0.822v for more than 18 s will trip the circuit breaker. the circuit breaker can also be made to trip by externally forcing the bidirectional fault pin below 0.816v. the fault pin has 35mv of hysteresis. an internal glitch filter of 15 s filters out noise on the fault pin. the slow comparator of channel n trips the circuit breaker if v rsense n = (v cc n C v sense n ) is greater than its 25mv threshold for more than 15 s. there may be applications where this inherent response time is not long enough, for example, because of excessive supply voltage noise. to adjust the response time of the slow comparator, a capaci- tor can be connected from the filter pin to gnd. if this pin is left unused, each slow comparators delay defaults to 15 s. during normal operation, the filter output pin is held low by an internal 1.8 a pull-down current source. during an overcurrent condition on either channel as shown in figure 6, the 1.8 a pull-down on the filter pin becomes an internal 105 a pull-up and c filter charges up. once the filter pin voltage ramps past its low-to- high threshold of 1.24v at time point 2, the electronic circuit breaker trips and the ltc4221 shuts down. the filter pins internal 1.8 a pull-down discharges c filter and holds filter low. each slow comparators response time from an overcurrent fault condition is: t vc a s filter filter = 124 105 15 .? (1) intermittent overloads may exceed the current limit as in figure 7, but if the duration is sufficiently short, the filter pin may not reach the v filter(th) threshold and the ltc4221 will not shut down. to handle this situation, the filter discharges with 1.8 a whenever both v rsense are below 25mv. any intermittent overload with an aggregate applicatio s i for atio wu uu figure 7. multiple intermittent overcurrent condition a1 b1 a2 b2 a3 b3 ~25mv/r sense1 ~25mv/r sense2 circuit breaker trips 1.8 a 1.8 a 4221 f07 1.8 a 105 a 105 a 105 a i load1 i load2 v filter v gate 1.24v 1.8 a slow comparator trip slow comparator trip slow comparator trip figure 6. a continuous fault timing 1.24v 12 normal slow comparator trip v filter circuit breaker trips. gate1, gate2 and fault pull low 1.8 a 1.8 a 4221 f06 1.8 a 105 a
17 ltc4221 4221fa duty cycle of more than 1.8% will eventually trip the circuit breaker. figure 8 shows the circuit breaker response time in seconds normalized to 1 f. the asymmetric charging and discharging of filter is a fair gauge of mosfet heating. t cf v ad a filter 124 105 1 8 . ?C. (2) the fast comparators trip the circuit breaker to protect against fast load overcurrents if v rsense is greater than v sense(fc) (100mv) for 1 s. the response time of each fast comparator is fixed at 1 s nominal. the timing diagram in figure 9 illustrates the operation of the ltc4221 when the load current conditions cause v rsense of channel 1 to ex- ceed 100mv for more than 1 s between time points 7 and 8. figure 9 also illustrates when the ltc4221s electronic circuit breaker is armed. after the initial timing cycle, it is armed at time point 3. arming the circuit breaker at time point 3 ensures that the system is protected against an over- current condition during the channel start-up cycle. at time point 4, the slow comparators are armed when the internal control loop is disengaged. autoretry after a fault once the ltc4221 circuit breaker is tripped, fault is latched low and both gate pins are pulled to ground. to clear the internal fault latch and to restart the ltc4221, its on1 pin must be pulsed below its reset threshold (v on(reset) = 0.4v) for at least 15 s. applicatio s i for atio wu uu timer fault filter on n 0.851v gate n sense n v out n reset initial timing 2 1 1.9 a v tmr(l) v tmr(h) electronic circuit breaker armed slow comparators armed 3 20 a 20 a 1.8 a 0.4v 105 a 9.5 a v filter(th) v sense(fc) v sense(sc) 45 6 7 8 9 reset 4221 f09 channel start-up normal fault figure 9. fast comparator trip timing waveforms figure 8. circuit breaker filter response for intermittent overload overload duty cycle, d (%) normalized response time (s/ f) 1 0.01 0.1 0 102030405060708090100 4221 f08 t c filter ( f) 1.24v 105 ? d C 1.8 =
18 ltc4221 4221fa the ltc4221 can also be configured to automatically retry after a fault condition. as shown in figure 10, the fault (which has an internal 3.8 a pull-up current source) and both on pins are connected together. the timing diagram in figure 11 illustrates a simultaneous start-up sequence where the ltc4221 is powered up into a load overcurrent condition on channel 1. after the slow comparators are armed at the end of the start-up cycle at time point 4, slow comparator 1 immediately trips and filter ramps up. filter ramps past its high threshold at time point 6 and trips the circuit breaker. fault and both on pins are pulled low by an internal n-channel mosfet and over- shoots below the 0.4v reset threshold of the on1 pin. once on1 < 0.4v for more than 15 s, the internal fault applicatio s i for atio wu uu + v cc1 on1 sense1 on2 fault r f2 15k ltc4221* gate1 fb1 4221 f10 1 16 7 10 9 c timer 1 f gnd timer r f1 56k v out1 3.3v 5a v out2 2.5v 5a q1 irf7413 r sense1 0.004 c load1 8 c filter 1nf filter z1 q2: 2n7002lt1 z1: smaj10 * additional details omitted for clarity r x1 10 c x1 100nf c on1 0.47 f r1 1m long v cc1 long pcb edge connector (male) short backplane connector (female) long v cc2 fault figure 10. using fault to configure autoretry 2 13456789 20 a electronic circuit breaker armed 20 a2 a 1.8 a 0.4v 0.4v 0.851v v filter(th) v sense(fc) v sense(sc) 9.5 a 105 a 1.9 a v tmr(l) v tmr(h) 0.851v timer on n , fault filter gate1 sense1 v out1 reset channel start-up filter ramp reset t on t initial off initial timing 4221 f11 initial timing t initial t startup t filter slow comparators armed figure 11. autoretry timing waveforms
19 ltc4221 4221fa latch is cleared and the fault pin sources a 3.8 a pull-up current to charge up c on1 . the typical delay t on is : tvv c a on on = () 0 851 0 4 38 1 .C.? . (3) as shown in the timing diagram of figure 11, the autoretry circuitry will attempt to restart the ltc4221 with a duty cycle: duty cycle = t startup + () ++ + t tt t t filter on initial startup filter ?% 100 (4) t filter is defined in equation 1 and t on is defined in equa- tion 3. t initial , the initial timing cycle delay, is given in equation 9 located in the initial timing cycle section. t startup , the start-up cycle delay, is given in equation 10 and found in the start-up cycle without current limit section. using the capacitor values as shown in figure 10, the autoretry duty cycle works out to be approximately 6%. sense resistor consideration the fault current level at which the ltc4221s internal electronic circuit breaker trips is determined by sense resistors connected between each channels v cc and sense pins. for both channels, the slow comparator trip current and the fast comparator trip current are given by equations (5) and (6) respectively. i v r mv r trip sc sense sc sense sense () () == 25 (5) i v r mv r trip fc sense fc sense sense () () == 100 (6) the power rating of the sense resistor should be rated at the fault current level. table 1 in the appendix lists some common sense resistors. for proper circuit breaker operation, kelvin-sense pcb connections between the sense resistor and each channels v cc and sense pins are strongly recommended. the drawing in figure 12 illustrates the connections between the ltc4221 and the sense resistor. pcb layout should be balanced and symmetrical to minimize wiring errors. in addition, the pcb layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation. calculating current limit for a selected r sense , the load current must not exceed i trip(sc) . the minimum i trip(sc) is given by equation 7: i v r mv r trip scmin sense scmin sense max sense max () () () () . == 20 5 (7) where rr r sense max sense tol () ? =+ ? ? ? ? ? ? 1 100 the maximum i trip(sc) is given by equation 8: i v r mv r trip scmax sense scmax sense min sense min () () () () . == 29 5 (8) where rr r sense min sense tol () ?C = ? ? ? ? ? ? 1 100 if a 7m sense resistor with 1% tolerance is used for current limiting, the nominal slow comparator trip current is 3.57a. from equations 7 and 8, i trip(scmin) = 2.9a and i trip(scmax) = 4.26a. for proper operation, the minimum i trip(sc) must exceed the circuit maximum operating load current. for reliability purposes, the operation at the maximum trip current must be evaluated carefully. if necessary, two resistors with the same r tol can be connected in parallel to yield a nominal r sense value that fits the circuit requirements. applicatio s i for atio wu uu sense resistor to v cc n to sense n current flow to load current flow to load track width w: 0.03" per amp on 1oz copper w 4221 f12 figure 12. pcb connections to the sense resistor
20 ltc4221 4221fa timer function the timer pin controls the initial cycle and the channel start-up cycles with an external capacitor, c timer . there are two comparator thresholds: v tmr(h) (1.234v) and v tmr(l) (0.4v). in addition, the pin has a 1.9 a pull-up current, a 20 a pull-up current and a n-channel mosfet pull-down. initial timing cycle when the card is being inserted into the bus connector, the long pins mate first which brings up the supplies at time point 1 of figure 13. the ltc4221 is in reset mode as the on1 pin is low. both gate pins and the timer pin are pulled low. at time point 2, the short pin makes contact and both on pins are pulled high. at this instant, a start-up check requires that both supply voltages be above uvlo, at least one on pin be above 0.851v, both gate pins < 0.4v and timer < 0.4v. when these four conditions are fulfilled, the initial cycle begins and the timer pin is pulled high with 1.9 a. at time point 3, the timer reaches v tmr(h) and is pulled down below v tmr(l) by the n- channel mosfet pull-down, ending the initial cycle at time point 4. the initial cycle delay is: tv c a initial timer = 1 234 19 .? . (9) at time point 4, the ltc4221 checks whether the filter pin is <1.24v and fault is > 0.851v. if both conditions are met, a channel start-up cycle commences. start-up cycle without current limit during a channel start-up cycle, the timer pin ramps up with a 20 a internal pull-up so the start-up cycle delay is: tvv c a startup timer = () 1 234 0 4 20 .C.? (10) at the beginning of the start-up timing cycle (time point 4), the ltc4221s electronic circuit breaker is armed and each channel has an internal 9.5 a current source working with an internal charge pump to provide the gate drive to its external pass transistor. at time point 5, gate1 reaches the external pass transistor threshold and v out1 starts to follow the gate1 ramp-up. if the inrush current is below current limit, gate1 ramps at a constant rate of: v t i c gate gate gate (11) where c gate is the total capacitance at the gate1 pin. the inrush current through r sense1 can be divided into two components; i cload due to the total load capacitance c load and i load due to the noncapacitive load elements. the load bypass capacitance typically dominates c load . for a successful channel start-up without current limit, i inrush < active current limit. due to the voltage follower configuration, the v out1 ramp rate approximately tracks v gate1 . the inrush current during a start-up cycle without current limit is : ic v t i ic v t i ic i c i inrush load out load inrush load gate load inrush load gate gate load = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (12) at time point 6, v out1 is approximately v cc1 but gate1 ramp-up continues until it reaches a maximum voltage. this maximum voltage is determined either by the charge pump or the internal clamp. applicatio s i for atio wu uu 1.234v v cc n v out1 on n timer gate1 reset state initial timing channel 1 start-up normal 20 a 9.5 a 0.4v v th discharge by load 4221 f13 0.851v 0.4v 12 345 6 7 1.9 a figure 13. channel 1 start-up without current limit
21 ltc4221 4221fa 0.4v v th 1.234v 1.9 a 20 a <9.5 a 9.5 a 9.5 a discharge by load 4221 f14 0.851v 0.4v 1.234v 12 v cc n v on n v timer v gate2 v out2 i rsense2 3456 78 9 a regulated at 25mv/r sense regulated at v sense(acl) (t)/r sense reset state initial timing channel 2 start-up normal cycle start-up cycle with current limit during a channel start-up cycle, if the inrush current as according to equation (12) is large enough to cause a voltage drop greater than the active current limit threshold (v sense(acl) ) across the sense resistor, an internal servo loop controls the operation of the 9.5 a current source at the gate pin to regulate the load current to: i v r inrush sense acl sense = () (13) the active current limit threshold for channel n has a component controlled by the voltage at the fb n pin. when fb n = 0v, v sense(acl) = 9mv. as v out n and fb n ramp up, v sense(acl) increases linearly until fb n reaches 0.5v, where v sense(acl) saturates at 25mv. in this fashion, the inrush current is controlled by this foldback limiting that tends to keep the power dissipation in the external mosfet constant during the start-up cycle. the timing diagram in figure 14 illustrates the operation of the ltc4221 in a channel start-up cycle with limited inrush current as described by equation 13. between time points 5 and 6, the gate2 pin ramps up with i gate = 9.5 a. at time point 6, the inrush current increases enough to trip v sense(acl) (t) and an internal servo loop engages, limiting the inrush current to the level as in equation 13 by decreasing i gate (<9.5 a). as a result, the ramp rate of both v gate2 and v out2 decreases and v sense2 increases linearly until it saturates at 25mv at time point 7. at time point 8, the external mosfet enters triode operation. i inrush drops as the ramp rate of v out2 falls below that of v gate2 so i gate reverts back to 9.5 a. at time point 9, the internal servo loop to control i inrush is disengaged and channel 2 slow comparator is armed, ending the channel 2 start-up cycle. so if c load2 is not fully charged up at this point, i inrush will be subject to the slow comparator threshold and actions as outlined in the electronic circuit breaker section. for a successful channel start-up, the current limited part of the v out ramp-up (time points 6 and 8 of figure 14) must not exceed the sum of start-up cycle delay as given by equation 10 and the slow comparator response time as given by equation 1. an example of an unsuccessful start-up is figure 11 which shows a channel powering up into an overcurrrent at the load. the fast comparators of both channels are armed at the end of the initial timing cycle at time point 4 of figure 14. if a short circuit during the start-up cycle overrides the servo loop and causes v rsense of either channel to exceed 100mv for more than 1 s, the electronic circuit breaker trips and the ltc4221 enters the fault state. frequency compensation at start-up cycle if a channels external gate input capacitance (c iss ) is greater than 600pf, no external gate capacitor is required at gate to stabilize the internal current-limiting loop dur- ing start-up with current limit. the servo loop that controls the external mosfet during current limiting has a unity- gain frequency of about 105khz and phase margin of 80 for external mosfet gate input capacitances to 2.5nf. power mosfet power mosfets can be classified by r ds(on) at v gs gate drive ratings of 10v, 4.5v, 2.5v and 1.8v. those rated for r ds(on) at 10v v gs usually have a higher v gs absolute maximum rating than those at 4.5v and 2.5v. at low applicatio s i for atio wu uu figure 14. channel 2 start-up with current limit
22 ltc4221 4221fa supply voltages, the ltc4221 can drive any mosfet rated with 4.5v or 2.5v gate drive. for higher supply voltages up to 13.5v, the ltc4221 can drive any mosfet rated with a 10v or 4.5v gate drive. the selected mosfet should fulfill two v gs criteria: 1. positive v gs absolute maximum rating > ltc4221s maximum v gate . 2. negative v gs absolute maximum rating > supply volt- age. the gate of the mosfet can discharge faster than v out when shutting down the mosfet with a large c load . if one of the conditions cannot be met, an external zener clamp shown on figure 15 can be used. the clamp network is connected from each channels gate to the v out pins. v gs is clamped in both directions and r g limits the current flow into the gate n pins internal zener clamp during transient events. a mosfet with a v gs absolute maximum rating of 20v meets the two criteria for all the ltc4221 application ranges from 1v to 13.5v. typically most 10v gate rated mosfets have v gs absolute maximum ratings of 20v or greater, so no external v gs zener clamp is needed. there are 4.5v gate rated mosfets with v gs absolute maximum ratings of 20v. in addition to the mosfet gate drive rating and v gs absolute maximum rating, other criteria such as v bdss , i d(max) , r ds(on) , p d , ja , t j(max) and maximum safe operating area (soa) should also be carefully reviewed. v bdss should exceed the maximum supply voltage inclu- sive of spikes and ringing. i d(max) must exceed the maxi- mum short-circuit current in the channel during a fault condition. r ds(on) determines the mosfet v ds which to- gether with v rsense yields an error in the v out voltage. for example, at 1v v cc2 , v ds + v rsense2 = 50mv gives a 5% v out2 error. at higher v cc voltages the v ds requirement can be relaxed in which case the mosfets thermal require- ments (p d , t j(max) , soa) may limit the value of r ds(on) . the power dissipated in the mosfet is (i load ) 2 ? r ds(on) and this should be less than the maximum power dissipa- tion, p d , allowed in that package. given power dissipation, the mosfet junction temperature, t j can be computed from the operating temperature (t a ) and the mosfet package thermal resistance ( ja ). the operating t j should be less than the t j(max) specification. the v ds ? i load figure must also be well within the manufacturers recom- mended safe operating area (soa) with sufficient margin. these three thermal parameters must not be exceeded for all conditions in a channel including normal mode opera- tion, start-up with or without current limit, fault and autoretry after a fault. to ensure a reliable design, fault tests should be evaluated in the laboratory. v cc transient protection good engineering practice calls for bypassing the supply rail of any analog circuit. bypass capacitors are often placed at the supply connection of every active device, in addition to one or more large value bulk bypass capacitors per supply rail. if power is connected abruptly, the large bypass capacitors slow the rate of rise of the supply voltage and heavily damp any parasitic resonance of lead or pc track inductance working against the supply bypass capacitors. the opposite is true for ltc4221 hot swap circuits mounted on plug-in cards since controlling the surge current to bypass capacitors at plug-in is the primary motivation for the hot swap controller. in most cases, there is no supply bypass capacitor present on the pow- ered supply voltage side of the mosfet switch. although wire harness, backplane and pcb trace inductances are usually small, these can create large spikes when large currents are suddenly drawn, cut off or limited. abrupt intervention can prevent subsequent damage caused by a catastrophic fault but it does cause a large supply tran- sient. these ringing transients appear as a fast edge on applicatio s i for atio wu uu *user selected voltage clamp (a low bias current zener diode is recommended) 1n4688 (5v) 1n4692 (7v): logic-level mosfet 1n4695 (9v) 1n4702 (15v): standard-level mosfet r sense gate 4221 f15 q1 r g 200 d1* d2* v cc v out figure 15. gate protection zener clamp
23 ltc4221 4221fa the input supply line, exhibiting a peak overshoot to 2.5 times the steady-state value. this peak is followed by a damped sinusoidal response whose duration and period are dependent on the resonant circuit parameters. this can cause detrimental damage to board components unless measures are taken. the energy stored in the lead/trace inductance is easily controlled with snubbers and/or transient voltage sup- pressors. even when ferrite beads are used for electro- magnetic interference (emi) control, the low saturating current of ferrite will not pose a major problem if the transient voltage suppressors with adequate ratings are used. the transient associated with a gate turn off can be controlled with a snubber and/or transient voltage sup- pressor. snubbers such as rc networks are effective especially at low voltage supplies. the choice of rc is usually determined experimentally. the value of the snub- ber capacitor is usually chosen between 10 to 100 times the mosfet c oss . the value of the snubber resistor is typically between 3 to 100 . when the supply exceeds 7v or emi beads exist in the wire harness, a transient voltage suppressor and snubber are recommended to clip off large spikes and reduce the ringing. for supply volt- ages of 6v or below, a snubber network should be suffi- cient to protect against transient voltages. these protection networks should be mounted very close to each of ltc4221s two supply voltages using short lead lengths to minimize lead inductance. this is shown schematically in the typical application on the front page of this data sheet. in many cases, a simple short-circuit test can be per- formed to determine the need of the transient voltage suppressor. additional overvoltage protection is provided by the fb n pins. applicatio s i for atio wu uu pcb layout considerations a recommended layout for the sense resistors, the power mosfets, v cc transient protection devices and gate drive components around the ltc4221 is shown in figure 16. for proper operation of the ltc4221s elec- tronic circuit breaker, a 4-wire kelvin connection to each sense resistor is used. also, pcb layout for the external n-channel mosfets emphasizes optimal thermal man- agement of mosfet power dissipation to keep ja as low as possible. the v cc transient protection devices are positioned close to the supply pins to reduce lead induc- tance and thus overshoot voltage. in hot swap applications where load currents can reach 10a or more, pcb track width must be appropriately sized to keep track resistance and temperature rise to a mini- mum. consult appendix a of ltc application note 69 for details on sizing and calculating trace resistances as a function of copper thickness. in the majority of applications, it will be necessary to use plated-through vias to make circuit connections from component layers to power and ground layers internal to the pc board. for 1oz copper foil plating, a good starting point is 1a of dc current per via, making sure the via is properly dimensioned so that solder completely fills any void. for other plating thicknesses, check with your pcb fabrication facility.
24 ltc4221 4221fa applicatio s i for atio wu uu figure 16. recommended layout for ltc4221 r sense , power mosfets and feedback networks g w ? ? ? ? ? ? ? ? ? ? power mosfet so-8 power mosfet so-8 note: drawing is not to scale *additional details omitted for clarity r sense2 r sense1 track width w current flow to load channel 2 output s s s r f3 r f4 vias bottom layer and gnd trace vias gnd to load d d d d ltc4221* g s s s d d d d 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 on1 v cc1 sense1 gate1 fb1 pwrgd1 fault filter on2 v cc2 sense2 gate2 fb2 pwrgd2 gnd timer r f2 r f1 4221 f16 r4 r3 r1 c x1 r2 z1 r x1 r x2 z2 c x2 w channel 2 input channel 1 output channel 1 input gnd current flow to load current flow to load current flow to load w c timer c filter appe dix u table 1 lists some current sense resistors that can be used with the circuit breaker. table 2 lists some power mosfets that are available. table 3 lists the web sites of several manufacturers. since this information is subject to change, please verify the part numbers with the manufacturer. table 1. sense resistor selection guide current limit value part number description manufacturer 1a lrf120601r020f 0.02 0.5w 1% resistor irc-tt 2.5a wsl25127l000f 0.007 1w 1% resistor vishay-dale 3.3a wsl25126l000f 0.006 1w 1% resistor vishay-dale 5a wsl25124l000f 0.004 1w 1% resistor vishay-dale 10a wsl25122l000f 0.002 1w 1% resistor vishay-dale 2a lrf120601r010f 0.01 0.5w 1% resistor irc-tt
25 ltc4221 4221fa typical applicatio s u simultaneous turn-on with autoretry function?ndividual current limits on2 fault gnd ltc4221 z1 z2 1 16 7 10 9 8 fb2 pwrgd2 pwrgd1 pwrgd2 v out1 5v 5a v out2 3.3v 2.5a pwrgd1 fb1 long long gnd long z1, z2: smaj10 timer filter 234151413 12 11 6 5 on1 v cc1 sense1 gate1 v cc2 sense2 gate2 v cc1 5v v cc2 3.3v backplane connector (female) pcb edge connector (male) r x1 10 r x2 10 r3 15k r2 21k r1 3.16k r f3 20k q2 irf7413 r f4 5.11k r pg2 10k r pg1 10k r f1 32.4k r f2 5.11k 4221 ta02 c x1 100nf c filter 1nf c timer 470nf c x2 100nf q1 irf7413 r sense1 0.004 r sense2 0.007 appe dix u table 2. n-channel selection guide current level (a) part number description manufacturer 0 to 2 mmdf3n02hd dual n-channel so-8 on semiconductor r ds(on) = 0.1 , c iss = 455pf 2 to 5 mmsf5n02hd single n-channel so-8 on semiconductor r ds(on) = 0.025 , c iss = 1130pf 5 to 10 mtb50n06v single n-channel dd pak on semiconductor r ds(on) = 0.028 , c iss = 1570pf 10 to 20 mtb75n05hd single n-channel dd pak on semiconductor r ds(on) = 0.0095 , c iss = 2600pf table 3. manufacturers?web sites manufacturer web site temic semiconductor www.temic.com international rectifier www.irf.com on semiconductor www.onsemi.com harris semiconductor www.semi.harris.com irc-tt www.irctt.com vishay-dale www.vishay.com vishay-siliconix www.vishay.com diodes, inc. www.diodes.com
26 ltc4221 4221fa typical applicatio s u sequenced turn-on on2 fault gnd ltc4221 z1 z2 1 16 7 10 9 8 fb2 pwrgd2 pwrgd1 pwrgd2 v out1 3.3v 5a v out2 2.5v 5a fb1 long long gnd long z1, z2: smaj10 timer filter 234151413 12 11 6 5 on1 v cc1 sense1 gate1 v cc2 sense2 gate2 v cc1 3.3v v cc2 2.5v backplane connector (female) pcb edge connector (male) r x1 10 r x2 10 r3 14.3k r4 10k r2 21k r1 10k r f3 14.3k q2 irf7413 r f4 5.11k r pg2 10k r f1 20k r f2 5.11k 4221 ta04 c x1 100nf c filter 1nf c timer 470nf c x2 100nf q1 irf7413 r sense1 0.004 r sense2 0.004 simultaneous turn-on with autoretry function?inked current limits on2 fault gnd ltc4221 z1 z2 1 16 7 10 9 8 fb2 pwrgd2 pwrgd1 pwrgd2 v out1 3.3v 5a v out2 2.5v 5a pwrgd1 fb1 long long gnd long z1, z2: smaj10 timer filter 234151413 12 11 6 5 on1 v cc1 sense1 gate1 v cc2 sense2 gate2 v cc1 3.3v v cc2 2.5v backplane connector (female) pcb edge connector (male) r x1 10 r x2 10 r3 12.4k r2 16.5k r1 4.22k r f3 14.3k q2 irf7413 r f4 5.11k r pg2 10k r pg1 10k r f1 20k r f2 5.11k 4221 ta03 c x1 100nf c filter 1nf c timer 470nf c x2 100nf q1 irf7413 r sense1 0.004 r sense2 0.004
27 ltc4221 4221fa u package descriptio gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) gn16 (ssop) 0204 .016 C .050 (0.406 C 1.270) .015 .004 (0.38 0.10) 45 0 C 8 typ .007 C .0098 (0.178 C 0.249) .0532 C .0688 (1.35 C 1.75) .008 C .012 (0.203 C 0.305) typ .004 C .0098 (0.102 C 0.249) .0250 (0.635) bsc 12 3 4 5 6 7 8 .229 C .244 (5.817 C 6.198) .150 C .157** (3.810 C 3.988) 16 15 14 13 .189 C .196* (4.801 C 4.978) 12 11 10 9 .009 (0.229) ref .254 min recommended solder pad layout .150 C .165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale sequenced up/down, channel 1 up first, down last on2 fault gnd ltc4221 z1 z2 d1 1 16 7 10 9 8 fb2 pwrgd2 pwrgd1 v out1 3.3v 5a v out2 2.5v 5a fb1 long long short gnd fault long short d1: 1n4148 z1, z2: smaj10 timer filter 234151413 12 11 6 5 on1 v cc1 sense1 gate1 v cc2 sense2 gate2 v cc1 3.3v v cc2 2.5v on 0v to 3.3v or 3.3v to 0v backplane connector (female) pcb edge connector (male) r x1 10 r x2 10 r5 13k r3 8.06k r2 6.98k r4 10k r1 17.8k r f3 14.3k q2 irf7413 r f4 5.11k r f1 20k r f2 5.11k 4221 ta05 c x1 100nf c filter 1nf c timer 470nf c x2 100nf q1 irf7413 r sense1 0.004 r sense2 0.004 typical applicatio s u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
28 ltc4221 4221fa ? linear technology corporation 2004 lt 0707 rev a ?printed in the usa part number description comments ltc1421 2-channel, hot swap controller 24-pin, operates from 3v to 12v and supports C12v ltc1422 single channel, hot swap controller in so-8 operates from 2.7v to 12v, system reset output ltc1642 fault protected, hot swap controller operates up to 16.5v, overvoltage protection to 33v ltc1643al/ltc1643ah pci hot swap controllers 3.3v, 5v and 12v supplies ltc1645 dual channel hot swap controller operates from 1.2v to 12v, power sequencing ltc1647 dual channel, hot swap controller operates from 2.7v to 16.5v ltc4210 single channel, hot swap controller in sot-23 operates from 2.7v to 16.5v, multifunction current control ltc4211 single channel, hot swap controller in msop 2.5v to 16.5v, multifunction current control ltc4230 triple channel, hot swap controller 1.7v to 16.5v, multifunction current control ltc4251 C48v hot swap controller in s0t-23 C48v hot swap controller, active current limiting ltc4252 C48v hot swap controller in msop active current limiting with drain acceleration ltc4253 C48v hot swap controller and sequencer active current limiting with drain acceleration and three sequenced power good outputs related parts linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear-tech.com typical applicatio u sequenced up/down, channel 2 up first, down last on2 fault gnd ltc4221 z1 z2 d1 fb2 pwrgd2 pwrgd1 v out1 3.3v 5a v out2 2.5v 5a fb1 long long short gnd fault long short d1: 1n4148 z1, z2: smaj10 timer filter on1 v cc1 sense1 gate1 v cc2 sense2 gate2 v cc1 3.3v v cc2 2.5v on 0v to 3.3v or 3.3v to 0v backplane connector (female) pcb edge connector (male) r x1 10 r x2 10 r6 10k r3 12.1k r2 20.5k r4 23.2k r1 23.7k r5 9.53k r f3 14.3k q2 irf7413 r f4 5.11k r f1 20k r f2 5.11k 4221 ta06 c x1 100nf c filter 1nf c timer 470nf c x2 100nf q1 irf7413 r sense1 0.004 r sense2 0.004

▲Up To Search▲

Price & Availability of LTC4221-15

	To Download LTC4221-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .